Integrated circuits use conductive interconnects to wire together the individual devices on a semiconductor substrate, or to communicate externally to the integrated circuit. Interconnect metallization for vias and trenches may include aluminum alloys and copper. As device geometry continued to scale down to 45-nm-node technology and sub-45-nm technology, the requirement of continuous barrier/seed layer with good step coverage along high aspect ratio geometry to provide void free copper filling becomes challenging. The motivation to go to ultra thin and conformal barrier in 45-nm-node or sub-45-nm-technology is to reduce the barrier's impact on via and line resistance. However, poor adhesion of copper to the barrier layer could cause delamination between the barrier layer and copper during processing or thermal stressing that poses a concern on electro-migration (EM) and stress-induced voiding.
Barrier overhang 104 near top of the interconnect structure 100, as shown in FIG. 1A, by conventional physical vapor deposition (PVD) process is known to cause copper voids in metal lines or vias during copper gap-fill due to poor step coverage. The limited deposition of barrier material in the lower corners 103, as shown in FIG. 1A, is also a known problem to cause copper diffusion, EM problem, and stress-induced voiding. To ensure sufficient barrier material in the lower corners, sufficient barrier materials need to be deposited in the interconnect structures, which would result in copper voids during copper gap-fill. Therefore, a more conformal barrier deposition is needed.
In addition to step coverage concern, barrier layer, such as tantalum nitride (TaN), adheres well to dielectric layer 150; however, the adhesion between TaN and copper is poor. TaN is a good copper diffusion barrier. In contrast, barrier layer, such as tantalum (Ta), adheres well to copper, but not as well to the dielectric layer. Although it's possible to deposit a TaN layer 111 to line the interconnect structure to allow the TaN to contact the dielectric material 150 and to deposit a Ta layer afterwards for copper 113 to be in contact with Ta 112, as shown in FIG. 1B. The Ta layer acts as a liner layer or a glue layer to copper. However, a two-step process is more complicated and the deposition of the first TaN makes the aspect ratio of the interconnect structure even higher, which worsen the step coverage issue of the following Ta layer.
In view of the foregoing, there is a need for systems and processes that deposit a thin and conformal barrier layer that can yield good adhesion with the dielectric layer surrounding the interconnect structure and also with the copper layer that covers the barrier layer to improve yield and electro-migration performance and to reduce the risk of stress-induce voiding of copper interconnect.